In most processors, the number of available opcodes is limited by the length of the binary word which can be fetched into the instruction register. For instruction registers with a word length of N bits, 2.sup.N different opcodes can be read by the processor. Thus an 8 bit opcode set is limited to 256 opcodes. Encoding register designations within the opcodes, requires multiple opcodes for each register operation, leaving fewer opcodes available to encode other operations.
It is a goal of processor design to minimize the amount of time spent fetching data for operations, while keeping a maximum number of opcodes available for instructions.
One known technique is to increase the number of available opcodes by reading two consecutive words from the bus and joining them to form a single opcode. This technique effectively squares the number of available opcodes. But the reading of two words for every opcode slows the operation of the processor.
An alternative technique, disclosed in U.S. Pat. No. 4,346,437 of Blahut et al. and employed in the RCA-CDP1804AC processor, encodes some instructions with a one-word opcode and other instructions with a two-word opcode. Still, processor time is lost reading two opcode words for some of the instructions.
To avoid the proliferation of opcodes for register operations, the RCA-CDP1804AC microprocessor employs a single opcode independent of the register operated on for certain input/output (I/O) and arithmetic logic unit (ALU) instructions. The particular register on which an operation is performed is determined by a 4-bit "X" designator stored in the microprocessor. The value of the X designator is set by the instruction "SET X", which copies the contents of the N register to the X designator. Thus, the X designator enables a single opcode to encode an operation on any register designated by X; however, each time it is necessary to change the value of the X designator, a SET X instruction must be executed, which results in a loss of processor time.
Because operations are frequently performed on data registers, it is desirable for certain instructions to employ a single opcode for every possible combination of instruction and register. This is performed in the RCA-CDP1804AC microprocessor with the use of an "N" register. For each 8-bit opcode fetched by the CDPI804AC, the lower-order 4 bits of the instruction are loaded into the N register, and the value in the N register is used to designate the register operated on by the instruction.
There are processors with differing instruction sets and varying levels of performance. Programs are generally written for a particular processor and often cannot be run on any other processor. However, the development of most application programs requires a large investment of time and money. It is desirable to minimize those development costs should one wish to run a program on an alternative processor different from the one for which the program was designed. These costs of developing new programs can be reduced if the alternative processor is capable of interpreting and executing programs written for the original processor.
In particular, as a result of the popularity and endurance of the 6502 and related processors, a great number of programs have been written employing the 6502 instruction set. With the advance of technology, more sophisticated processors have been developed. It is beneficial, however, to maintain the ability to execute the vast library of programs written for the 6502 processor on a more advanced processor.
A "source" program which has been written for one processor may be executed on an alternative "host" processor with the use of a dispatch loop. A dispatch loop first fetches an opcode of the source program. From a table stored in memory, the dispatch loop then determines the address of a simulation routine consisting of host processor instructions which simulate the actions called for by the source instruction. The host processor jumps to the address of the simulation routine, executes the routine, and returns to the dispatch loop to fetch the next instruction. This technique, while offering accurate and flexible emulation, is particularly slow, in part due to the "overhead" of instructions which must be executed in order to operate the dispatch loop but which do not themselves simulate the source program.
It is known how to overcome the speed problems of the dispatch loop with the use of additional computer hardware componentry, as disclosed in U.S. Pat. Nos. 5,361,389 and 5,408,622, both of Jonathan Fitch. This solution, while improving the speed of emulation, results in a significant increase in hardware complexity, thus contravening the design of a compact computer system at a low cost.
Prior Art Processor--(FIG. 1)
As shown in FIG. 1, in a known computer design, a bus control 12 controls the flow of data, instructions, and addresses between processor 10 and a bus 14. Bus 14 enables communication between components of a computer, including processor 10, read-only memory (ROM) 16, random-access memory (RAM) 18, and input and output devices 20. Routines which direct the operation of processor 10 are stored as series of opcodes in ROM 16 and/or RAM 18. To execute these routines, processor 10 fetches an opcode by sending a memory address over bus 14 to specify a memory location in either ROM 16 or RAM 18. The opcode word at the addressed memory location is then sent over bus 14 to processor 10. An opcode is typically 8 bits, in which case the number of opcodes is limited to 256.
Opcodes fetched from bus 14 are interpreted by an instruction decode unit 22, which determines the operation or operations specified by the opcode. An arithmetic logic unit 24 then carries out the instructions on data contained in registers 26. A set of special purpose registers 28 is also provided, including an instruction pointer IP and a stack pointer SP. Instruction pointer IP supplies the address of the next opcode to be fetched from memory 16, 18 and is incremented (to point to the next opcode) each time an opcode is fetched. Flags 30, including sign flag S, overflow flag V, zero flag Z, and carry flag C are tested in conditional operations.